Part 2 Architecture
A. Binary Representations of Data
- Binary Representations of Octal, Decimal and Hexadecimal digits
- Binary Representation of Characters, ASCII code
- Representations of Signed and Unsigned Integers and Fractions
- Packed Decimal, 2's Complement and Signed Magnitude
- Representations of Fixed Point and Floating Point numbers
- IEEE Floating Point format
B. Design of Combinational functions and circuits
- Boolean Algebra, Truth Tables and Karnaugh Maps
- Gates, Combinational circuits, and timing delays
- Decoders, Multiplexers, Full and Half Adders, Full and Half Subtractors, Combinational Multiplier and Divider Circuits, and Logic Circuits, ROMs and PLAs
C. Design of Sequential functions and circuits
- State Diagrams, State Tables and Register Transfer Language Programs
- Flip-flops, Registers; the Clock and Timing Control
- Registers with various operations such as: Counters, Logical and Arithmetic Shift operations, and Parallel Load operations.
- Integer and Floating Point .Sequential Multiplier and Divider circuits
D. Register Transfer Language (RTL)
- Representation of Control functions and Microoperations
- Specification of Register and Memory transfers, Buses, Arithmetic and Logical operations
- Translation of an RTL program into a Logic Diagram
- Timing Signals and Control Signals
E. Performance and Cost Analysis
- Benchmarks, Performance Measures, Performance and Execution Time, Amdahl's law, Speedup, CPU Time, Clock Cycle Time and Clock Rate, Cycles per Instruction and Instruction Count
F. Instruction Set Principles
- Accumulator, Stack and General Purpose Architectures
- Register-Register (or Load-Store Architecture) and Register-Memory Architectures
- Operand Addressing Modes, Instruction Set Operations, Type and Size of Operands and the Encoding of an Instruction Set
- RISC versus CISC
G. Design and Performance Analysis of a non-Pipelined CPU
- An RTL Program Specifying the Fetching and Execution of Instructions
- Operand Address Decoding
- Interrupt Cycle
- Hard-Wired and Microprogrammed Control Units
- Microprogram Instructions and Formats
- Control Words
H. Design and Performance Analysis of a Pipelined CPU
- Relationship between an Instruction set and a Pipelined CPU
- Pipeline Registers
- Pipeline Data and Control Hazards
- Stalls
- Forwarding
- Instruction Scheduling, Delay Slots and a Delayed Branch
- Multi-cycle Operations and Exception Handling
I. Memory-Hierarchy Design and Performance Analysis
- Principle of Locality
- Cache, Main Memory and Secondary Memory
- Cache hit rate and time, miss rate and time, and miss penalty
- Direct, Associative, and Set Associative mappings
- Replacement Algorithms
- Write Through and Write back Caches
- Main Memory, the CPU-Memory Bus, Access time and Cycle time, and bandwidth
- Design of 1-Dimensional and 2-Dimensional RAMs and DRAMs
- Interleaved Memory and Memory Banks
- Virtual Memory
J. I/O and Storage System Design, and Performance Analysis
- Magnetic Disks
- I/O Buses, Bus Masters and Synchronous and Asynchronous Buses
- Data Transfers. Hand Shaking, Cycle Stealing, Bus Request and Acknowledge
- I/O programming and Interrupt Handling
- DMA and 10P
- I/O Performance Measures
K. Multiprocessors
Textbooks
- J. Hennessy & D. Patterson, Computer Architecture A Quantitative Approach, 2nd Edition, Morgan Kaufmann.
- J. Hayes, Computer Architecture, 2nd Edition, Hayes, McGraw-Hill.
- M.M. Mano, Computer System Architecture, 3rd Edition, Prentice Hall.
- D. Patterson and J. Hennessy, Computer Organization and Design, 3rd Edition, Morgan Kaufmann.
